Exemplary embodiments of the present invention relate to a technology for fabricating a semiconductor device, and more particularly, to a memory device.
Research has been conducted to develop next-generation memory devices that can replace a Dynamic Random Access Memory (DRAM) and a flash memory. Among the next-generation memory devices are Phase-change Random Access Memory (PRAM), Magnetic RAM (MRAM), Spin Transfer Torque RAM (STTRAM), Resistive RAM (ReRAM). The aforementioned next-generation memory devices are a kind of memory devices that store data based on a change in resistance. They have simple structures and great sensing current.
FIG. 1 is a plan view illustrating a conventional memory device.
Referring to FIG. 1, the memory device includes a memory unit 100, a first driving unit 101, and a second driving unit 102. The memory unit 100 includes a plurality of first conductive lines 11 and second conductive lines 12 crossing each other and a variable resistance unit (not shown) interposed between them. Memory cells C1 and C2 are disposed at the cross points between the first conductive lines 11 and the second conductive lines 12. The first driving unit 101 controls voltages/currents of the first conductive lines 11 and includes a plurality of first contacts 13 through which the plurality of the first conductive lines 11 are coupled with the first driving unit 101, and the second driving unit 102 controls voltages/currents of the second conductive lines 12 and includes a plurality of second contacts 14 through which the plurality of the second conductive lines 12 are coupled with the second driving unit 102.
The first driving unit 101 and the second driving unit 102 includes a plurality of transistors T, respectively, and each transistor T includes a gate 15 and junction regions 16 disposed on both sides of the gate 15. Here, the plurality of the first contacts 13 and plurality of the second contacts 14 are coupled with the junction regions 16 between the memory unit 100 and the gates 15, respectively, and the gaps between the gates 15 and the plurality of the first contacts 13 and the gaps between the gates 15 and the plurality of the second contacts 14 are the same. Also, the areas of the junction regions 16 coupled with the plurality of the first contacts 13 and the plurality of the second contacts 14 are all the same.
However, the memory device having the above-described structure has a feature that the resistance difference according to the positions within the memory unit 100 which may occur in the process of sensing and programming may deteriorate the accuracy of data.
More specifically, a first memory cell C1 is disposed at a position closest to the first driving unit 101 and the second driving unit 102 in the memory unit 100. A second memory cell C2 is disposed at a position farthest from the first driving unit 101 and the second driving unit 102 in the memory unit 100. Here, looking at the line resistances between the first and second memory cells C1 and C2 and the first and second driving units 101 and 102, the first memory cell C1 has the smallest line resistance, while the second memory cell C2 has the greatest line resistance. As described above, when the line resistance difference occurs according to the positions where the first and second memory cells C1 and C2 are disposed and the resistance of a variable resistance unit interposed between the first conductive lines 11 and the second conductive lines 12 is not vastly greater than the line resistance, oxygen saturation amount of the memory unit 100 may be increased.
Here, diverse methods have been suggested in order to address such features caused by the resistance difference according to the position within the memory unit 100. The methods include a method of decreasing the size of the memory unit 100, a method of decreasing the resistances of the first conductive lines 11 and the second conductive lines 12, and a method of increasing the resistance of the variable resistance unit. The aforementioned methods, however, may result in increasing chip size, complicating manufacturing process and production costs, and lowering on/off ratio of memory cells.